1. Technical Field of the Invention
This invention relates to an insulated gate semiconductor device with high voltage structure and its manufacturing method, especially to a technology to improve the breakdown voltage between a gate and a source as well as the breakdown voltage between a gate and a drain.
2. Background Art
The insulated gate semiconductor device of the prior art will be explained hereinafter by referring to FIG. 5. This type of insulated gate semiconductor device is generally called a MOS transistor. Here, the MOS transistor with a high voltage structure will be explained. This kind of MOS transistor is used as an output buffer for an LCD driver.
In FIG. 5, an N−type source layer 52 and an N−type drain layer 53 are deeply formed by thermal diffusion on the surface of a P type silicon substrate 51. The N−type source layer 52 and the N−type drain layer 53 are made of an N type diffusion layer of a relatively low impurity concentration. The region between the N−type source layer 52 and the N−type drain layer 53 is a channel region CH.
Reference numerals 54 and 55 denote thick gate oxide films formed by selective oxidation. The thick gate oxide film 54 is formed at the edge of the N−type drain layer 53, and the thick gate oxide film 55 is formed at the edge of the N−type source layer 52. Reference numeral 56 denotes a field oxide film formed simultaneously by the selective oxidation stated above. The thick gate oxide films 54, 55, and the field oxide film 56 are films that are generally called LOCOS.
Reference numeral 57 denotes a thin gate oxide film formed on the channel region CH of the MOS transistor. The thin gate oxide film 57 and the thick gate oxide films 54 and 55 make a unitary unit forming a gate oxide film. N+type source layer 58 is formed on the surface of the silicon substrate 51 between the thick oxide film 54 and the field oxide film 56. Likewise, N+type drain layer 59 is formed on the surface of the silicon substrate 51 between the thick oxide film 55 and the field oxide film 56. The N+type source layer 58 and the N+type drain layer 59 are made of an N type diffusion layer of a high impurity concentration. A gate electrode 60 covers the thin gate oxide film 57 and partially extends over the thick gate oxide films 54 and 55.
The structure of the MOS transistor described above can be summarized as follows. The edge of the gate electrode 60 is formed away from the N+type source layer 58 as well as away from the N+type drain layer 59. The region between the gate electrode 60 and the N+type source layer 58, and the region between the gate electrode 60 and the N+type drain layer 59 are called offset regions. In the offset regions, the thick gate oxide films 54 and 55 are formed. Under these thick gate oxide films 54 and 55, the N−type source layer 52 and the N−type drain layer 53 are formed on the surface of the semiconductor substrate 51. The N−type source layer 52 and the N−type drain layer 53 also extend to the area beneath the N+type source layer 58 and the N+type drain layer 59.
The structure described above provides an improvement in the breakdown voltage between the gate and the source because of the smaller electric field between the gate electrode 60 and the N+type source layer 58. In the same manner, the breakdown strength between the gate and the drain is also improved because of the smaller electric field between the gate electrode 60 and the N+type drain layer 59. Here, the breakdown voltage between the gate and the source is the voltage at which dielectric breakdown occurs between the gate and the source when a high voltage is applied to the gate. Likewise, the breakdown voltage between the gate and the drain is the voltage at which dielectric breakdown occurs between the gate and the drain when a high voltage is applied to the gate.
Also, this structure provides an improvement in the source breakdown voltage, the drain breakdown voltage and the breakdown voltage between the source and the drain. Here, the source breakdown voltage is the voltage at which breakdown occurs when a high voltage is applied to the source. Also, the drain breakdown voltage is the voltage at which breakdown occurs when a high voltage is applied to the drain. The breakdown strength between the source and the drain is the voltage at which breakdown occurs when a high voltage is applied between the source and the drain.
However, in the structure described above, the height gap h1 between the gate electrode 60 and the N+type source layer 58 or the N+type drain layer 59 is large, because the gate electrode 60 partially extends over the thick gate oxide films 54 and 55.
Thus, the flatness of the interlayer oxide film 61 is reduced since the interlayer oxide film made of BPSG film reflects the height gap h1, creating the height gap H1. Here, BPSG stands for boron phosphorus silicate glass.
The reduction in the flatness of the interlayer oxide film 61 also causes problems such as degraded processing accuracy of a wiring layer which is formed on the interlayer oxide film 61. When an aluminum wiring layer is formed on the interlayer oxide film 61, an aluminum layer is first formed on the interlayer oxide film 61 by a sputtering method. Then, a photoresist layer is formed on the aluminum layer.
Next, the photoresist layer is exposed by using a stepper. A development processing is performed to the photoresist layer, and the photoresist layer is then processed to have a certain amount of line width. When the interlayer oxide film 61 becomes less flat, the accuracy of the line widths of the photoresist layer after the development processing is also degraded.
Afterwards, etching is performed on the aluminum layer by using the processed photoresist layer as a mask for forming the aluminum wiring layer. However, the degraded accuracy of the line widths of the photoresist layer also leads to degraded accuracy in the line widths of the aluminum wiring layer. That is, the deterioration of the flatness of the interlayer oxide film 61 causes the degraded processing accuracy of the wiring layer.